Measurement and SPICE prediction of sub-picosecond clock jitter in A/D converters

We propose an innovative characterization technique that allows us to discriminate noise contributions due to jitter from other phenomena (voltage reference and substrate noise, high-amplitude effects) in A-to-D converters. The jitter estimated with this method closely matches that inferred from the signal-to-noise ratio at high input frequencies, where noise is dominated by the aperture uncertainty. At the sub-picosecond level required for the 14-b high-IF ADC under test, any off-chip disturbances substantially affect the accuracy of the measurement. In order to characterize the uncertainty, first the phase noise spectrum of the external clock source is measured and converted into jitter by way of a rigorous formula. Then, the timing ambiguity associated with the on-chip clock pre-amplification and distribution circuitry is simulated via standard Spice techniques, providing results in agreement with experimental evidence. The paper provides tools to isolate the main noise sources in the clock circuit, and optimize it for low jitter in the early simulation phase. Moreover, it arms the designer with a robust yet easy experimental method to assess the jitter value, and interpret the SNR data gathered from test silicon.