A logic-aware layout methodology to enhance the noise immunity of domino circuits

The circuit performance is increasingly affected by signal integrity as cross-talk becomes more significant with scaling down of feature sizes. Many attempts have been made to improve noise immunity, but all require the sacrifice of speed as a tradeoff. In some circuits, P/G network is used as shielding wires to avoid cross-talk while maintaining the desired speed, but the use of the network is inherently restricted by electromigration, IR drop, Ldi/dt noise, etc. We propose a novel methodology to enhance the noise immunity of domino circuits by reordering transistors as well as interconnects based on the functionality of the circuit. To the best of our knowledge, it is the first attempt to use the functionality of a circuit for the purpose of noise immunity enhancement. The methodology, named "Logic-Aware Layout Methodology" (LALM), is composed of a few sub-techniques and can be used to improve the signal integrity of domino circuits. Experimental results show that LALM is simple to apply yet useful to improve the noise immunity of domino circuits.