DocumentCode :
1563338
Title :
A highly scalable 3D chip for binary neural network classification applications
Author :
Bermak, Amine
Author_Institution :
Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, China
Volume :
5
fYear :
2003
Abstract :
This paper describes a 3D VLSI Chip for binary neural network classification applications. The 3D circuit includes three layers of MCM integrating 4 chips each making it a total of 12 chips integrated in a volume of (2 × 2 × 0.7)cm3. The architecture is scalable, and real-time binary neural network classifier systems could be built with one, two or all twelve chip solutions. Each basic chip includes an on-chip control unit for programming options of the neural network topology and precision. The system is modular and presents easy expansibility without requiring extra devices. Experimental test results showed that a full recall operation is obtained in less than 1.2μs for any topology with 4-bit or 8-bit precision while it is obtained in less than 2.2μs for any 16-bit precision. As a consequence the 3D chip is a very powerful reconfigurable and a multiprecision neural chip exhibiting a significant speed of 1.25 GCPS.
Keywords :
VLSI; neural chips; pattern classification; 16 bit; 4 bit; 8 bit; MCM; VLSI; binary neural network classification; expansibility; multiprecision neural chip; on-chip control unit; scalable 3D chip; Artificial neural networks; Costs; Gas detectors; Hardware; Integrated circuit interconnections; Network topology; Neural networks; Packaging; Power system interconnection; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN :
0-7803-7761-3
Type :
conf
DOI :
10.1109/ISCAS.2003.1206405
Filename :
1206405
Link To Document :
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