Power Consumption Management on FPGAs

During the last years, the number of hardware implementations based on Field Programmable Gate Arrays (FPGAs) is increasing because it satisfies the high speed of system and hardware cost constraints. FPGAs implementation allows the building of rapid prototypes reducing development times and board area. However, since FPGAs has been improved to satisfy speed and size constraints, it is not evident that these devices could satisfy low-power consumption constraint. Compared to ASICs, FPGAs are generally perceived as non low-power consumption devices, whose only advantage is programmability and more recently dynamic reconfigurability. In this work we present an study of dynamic and static power consumption of FPGAs that allows the designer to acquire a better understanding of how power consumption is generated and distributed inside the FPGAs. Based on these results, a genetic algorithm will be used to minimize critical long paths and optimize the internal resources during the Place & Route process in order to optimize power consumption while keeping a high performance.