Logic systems for path delay test generation

The authors present an algorithmic derivation of logic systems for solving path delay test problems. In these logic systems, the state of a signal represents any possible situation that can occur during two consecutive vectors. Starting from a set of valid input states, a state transition graph is constructed to enumerate all possible states produced by Boolean gates. Specifics of the test problem are used for distinguishability criteria and to minimize the number of states. For test generation in combinational or sequential circuits, the authors use the algorithm to obtain optimal logic systems. They define optimality as to the smallest number of logic states that provide the least possible ambiguity. The ten-value logic of Fuchs et al. is found to be optimal for generating tests for single path delay faults but gives ambiguous results for multiple path activation. A new 23-value logic is derived as an optimal system for solving the multiple path problem as well as the delay test generation problem of sequential circuits. The limitations and capabilities of various logic systems are illustrated