Title :
Efficient on-chip communications for data-flow IPs
Author :
Fraboulet, Antoine ; Risset, Tanguy
Author_Institution :
Citi, Insa-Lyon, Villeurbanne, France
Abstract :
We explain a systematic way of interfacing data-flow hardware accelerators (IP) for their integration in a system on chip. We abstract the communication behaviour of the data flow IP so as to provide basis for an interface generator. We also explain which parameter this interface generator has to take into account. We validate our interface mechanism by a cycle accurate bit accurate simulation of a SoC integrating a data-flow IP.
Keywords :
circuit simulation; computer interfaces; data flow computing; high level synthesis; parallel machines; system-on-chip; SoC simulation; data-flow IP; data-flow hardware accelerators; high level synthesis; interface generation; on-chip communications; system on chip; Acceleration; Circuits; Computer architecture; Energy consumption; Hardware; High level synthesis; Protocols; Signal design; Streaming media; System-on-a-chip;
Conference_Titel :
Application-Specific Systems, Architectures and Processors, 2004. Proceedings. 15th IEEE International Conference on
Print_ISBN :
0-7695-2226-2
DOI :
10.1109/ASAP.2004.1342479
