• DocumentCode
    1564338
  • Title

    Utilizing Design Layout Information to Improve Efficiency of SEM Defect Review Sampling

  • Author

    Jansen, Scott ; Florence, Glenn ; Perry, Alexa ; Fox, Steven

  • Author_Institution
    IBM Microelectron. Div., Hopewell Junction, NY
  • fYear
    2008
  • Firstpage
    69
  • Lastpage
    71
  • Abstract
    SEM review samples of bright field inspection results can be one or more orders of magnitude smaller than the defect count. Because of this, there is a risk of the sample set not adequately representing the actual yield risk of the defect population, especially if systematic defects are present. Furthermore, SEM review based on this method is often inefficient due to "SEM non-visual", nuisance defects, or dummy fill patterns dominating the sample Pareto. The quality of the defect Pareto can be significantly improved using design based binning, or DBB. DBB couples layout information from design data with the relative location of each detected defect. This enables binning by key features of the pattern geometry surrounding the defect, thus providing more information about the yield risk of that defect. This paper describes the various components of DBB technology, and shows examples of improving SEM review efficiency by employing DBB to effectively bin out nuisance and other systematic defect types.
  • Keywords
    Pareto analysis; circuit layout; scanning electron microscopy; SEM defects; bright field inspection; design based binning; design layout information; layout information; nuisance defects; pattern geometry; sample Pareto quality; Information geometry; Inspection; Libraries; Mathematical model; Microelectronics; Pattern analysis; Process design; Sampling methods; Semiconductor device manufacture; Semiconductor device modeling; 2800; DBB; DBC; DBG; DCI; Defect Inspection; Design Based Binning; KLA-Tencor; design based classification; design based grouping; design criticality index;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Advanced Semiconductor Manufacturing Conference, 2008. ASMC 2008. IEEE/SEMI
  • Conference_Location
    Cambridge, MA
  • ISSN
    1078-8743
  • Print_ISBN
    978-1-4244-1964-7
  • Electronic_ISBN
    1078-8743
  • Type

    conf

  • DOI
    10.1109/ASMC.2008.4529011
  • Filename
    4529011