Yield Optimization with Model Based DFM

This paper will present a new methodology to define and optimize design for manufacturability (DfM) for system-on-chip product families. We developed a set of models correlating layout features with yield loss due to lithography, particle, and planarity constraints. Layout enhancements to mitigate these constraints result in more pronounced yield improvement, when performed in a local environment, case-by-case, rather than by automated routines at chip level. Model correlation for all three yield-limiting factors will help minimize the die area while using recommended rules (RR) with values larger than their manufacturable minima defined by design rules (DR).