DocumentCode
1564570
Title
REGGEN-Test pattern generation on register transfer level
Author
Magdolen, A. ; Bezakova, J. ; Gramatova, E. ; Fischerova, M.
Author_Institution
Inst. of Comput. Syst., Slovak Acad. of Sci., Bratislava, Slovakia
fYear
1993
Firstpage
259
Lastpage
264
Abstract
The authors describe the functional test generator REGGEN on a register transfer level. The technique of the symbolic simulation was modified by new rules to simplify symbolic expressions. In the REGGEN system a fault simulator at the RT level is also implemented. The efficiency of the REGGEN system has been proved on several gate arrays
Keywords
VLSI; automatic test equipment; design for testability; integrated circuit testing; integrated logic circuits; logic arrays; logic partitioning; logic testing; symbol manipulation; C-language; REGGEN; Test pattern generation; VLSI; fault simulator; functional test generator; gate arrays; register transfer; symbolic simulation; Algorithm design and analysis; Circuit faults; Circuit testing; Computational modeling; Digital circuits; Logic testing; Registers; System testing; Test pattern generators; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1993, with EURO-VHDL '93. Proceedings EURO-DAC '93., European
Conference_Location
Hamburg
Print_ISBN
0-8186-4350-1
Type
conf
DOI
10.1109/EURDAC.1993.410647
Filename
410647
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