90nm Games Processor Wafer to Module Power Yield Optimization

When fabricating a high volume games processor (CPU) for the consumer market, due to the cost of the module package, it is important to optimize the functional yield loss between the wafer die and the finished module package. For a performance CPU in a mature 90 nm technology the primary yield drivers can be power and performance. A functional power Iddq screen test method is presented here that decreases yield loss across functional test sectors by minimizing the impact of process variation for device gate leakage.