Topological and Model Based approach to Native Conflicts correction and pitch decomposition for Double Patterning

Double patterning (DP) is one of the main enabling technologies for expanding photolithography beyond 40 nm technology node. Geometrical pitch split is the core of DP. It is known and reviewed in this paper that not all sub- resolution layouts can be successfully split to two DP masks, so a method for early design for manufacturability (DFM) check and correction is strongly required. New accurate, efficient and Litho- aware methods for DP also minimize number of split errors and "false alarms" typical for rule-based DP mask data preparation. in this paper we propose the topological approach (model assisted topological rules check, MTRC) to the pitch decomposition for double patterning based on litho process modeling and real litho resolution of a process. This method detects features below a resolution limit of a process with the fast and accurate Tachyon litho modeling and automatically classifies them as either DP-friendly or DP-unfriendly (native conflicts) cases. MTRC helps to improve DP-unfriendly designs in optimal way by highlighting them at early stage. We also discussed how to find the best DFM redesign solution for a NC. This method uses the same printability criteria with MTRC and evaluates possible NC solution candidates according the best Litho manufacturability. Chip area penalty was also considered. The second part of the paper explains the model based DP pitch decomposition algorithm based on layout printability. It performs accurate and efficient split of various patterns with kl<0.25 to two masks with kl>0.25 as an integrated part of the Mask Data Preparation flow. The analysis of performance of the complex MB DP split approach mentioned above was performed on a selection of clips representing typical Flash, DRAM, SRAM and Logic polygon shapes. The results, achievements and known issues are discussed.