TCAD: a 27 MHz 8×8 discrete cosine transform chip

Author

Carlach, J.C. ; Penard, P. ; Sicre, J.L.

Author_Institution

Centre Commun. d´´Etudes de Telediffusion et de Telecommun., Cesson-Sevigne, France

fYear

1989

Firstpage

2429

Abstract

The circuit performs two-dimensional forward and inverse discrete cosine transform (DCT) on 8×8 blocks of data. Its implementation is based on the row-column decomposition scheme. A memory look-up approach combined with bit-serial structures is used to compute each one-dimensional DCT. A register-based transposition stage maintains the serial representation of the data after the first one-dimensional transform. This 50000-transistor circuit only uses read-only memories, registers, and adders. A pipeline architecture and a very regular layout lead to high-speed performances up to digital TV rates. The 32-pin version of the circuit accepts 9-bit pixel input and produces 12-bit coefficients in forward mode and vice-versa for inverse DCT mode. Its area is 26 mm² for a 1.2-μm CMOS technology

Keywords

CMOS integrated circuits; digital signal processing chips; transforms; 1.2 micron; 27 MHz; 2D DCT; CMOS technology; HF; ROM; adders; bit-serial structures; digital TV rates; discrete cosine transform chip; forward DCT; inverse DCT; inverse discrete cosine transform; memory look-up; pipeline architecture; read-only memories; register-based transposition stage; row-column decomposition; Adders; Arithmetic; Circuits; Concurrent computing; Convolution; Discrete cosine transforms; Matrix decomposition; Polynomials; Read only memory; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 1989. ICASSP-89., 1989 International Conference on

Conference_Location

Glasgow

ISSN

1520-6149

Type

conf

DOI

10.1109/ICASSP.1989.266958

Filename

266958