Title :
A single chip VLSI chrominance/luminance separator based on a silicon compiler
Author :
Miyazaki, T. ; Nishitani, T. ; Aikoh, S. ; Ishikawa, M. ; Yoshimura, T. ; Mitsuhashi, K. ; Furuichi, M.
Author_Institution :
NEC Corp., Kawasaki, Japan
Abstract :
The authors present a single-chip VLSI chrominance/luminance (Y/C) separator that is economically fabricated for NTSC TV signals at 13.5-MHz CCIR standard sampling rate. In order to realize compactness and low power dissipation, two FIR filter architectures and a multiplier structure are proposed. A silicon compiler, which uses these structures, also contributes to fast and error-free VLSI development. The Y/C separator chip has 10.4-mm×11.7-mm die size and attains about 860-MOPS operating speed
Keywords :
VLSI; circuit layout CAD; digital filters; digital signal processing chips; silicon; video signals; 13.5 MHz; 860 MFLOPS; CCIR standard sampling rate; FIR filter architectures; HF; NTSC TV signals; Si compiler; VLSI chrominance/luminance separator; multiplier structure; Band pass filters; Delay; Digital filters; Finite impulse response filter; Particle separators; Sampling methods; Signal processing; Silicon compiler; Transversal filters; Very large scale integration;
Conference_Titel :
Acoustics, Speech, and Signal Processing, 1989. ICASSP-89., 1989 International Conference on
Conference_Location :
Glasgow
DOI :
10.1109/ICASSP.1989.266959
