Two-level pipeline design for image resampling

The authors consider two implementation techniques for building a high-performance image-resampler VLSI chip. First, a two-level pipelined systolic array is designed for image resampling to give high parallelism in computation and high feasibility for VLSI implementation. Second, a modified two-pass resampling scheme is used to decrease the amount of required storage and increase the concurrency between two resampling passes. With the two techniques, the system can provide a throughput of one pixel in a clock period smaller than that for an adder