Algorithms and architecture of a VLSI signal processor for ANSI standard ISDN transceiver

The authors discuss major issues related to algorithms and architecture of the transceiver system and be the signal processor that they designed and implemented in a single VLSI chip. The functions of each block are described in the context of the overall system. The ideas behind their algorithms and architectural design are summarized. While the main focus of this study is on the signal processor, a companion analog chip in the transceiver performs certain front-end processing and is briefly summarized. The transmitter is entirely an analog implementation, except for scrambling. It consists of a D/A converter and a second-order Butterworth filter, followed by a line driver that feeds line pulses to the hybrid. A/D conversion at the receiver is done by a sigma-delta modulator with a double integration loop, which places the quantization noise at high frequencies mostly outside the baseband