The Motorola DSP 96002 IEEE floating-point digital signal processor

Author

Kloker, Kevin L. ; Lindsley, Brett ; Liberman, Sergio ; Marino, Paul ; Rushinek, Elchanan ; Hillman, Gatth D.

Author_Institution

Motorola Inc., Schaumburg, IL, USA

fYear

1989

Firstpage

2480

Abstract

A description is given of a dual-bus, user-programmable, CMOS digital signal processor that implements the IEEE 754-1985 standard for binary floating-point arithmetic. Peak performance is 13.5 MIPS and 40.5 MFLOPS with a 27 MHz clock. Designed for symmetric multiprocessing, the dual buses are programmable and functionally identical. CPU data, interrupts, and DMA blocks can be directly communicated between 96002s, without using any external memory. Circuitry on each external port identifies the fast access modes of dynamic memories, giving near-static RAM performance with low-cost DRAM/VRAM devices. The 96002 is based on a superset of Motorola´´ DSP56000/1 fixed-point DSP architecture and is software-compatible with DSP56000/1 source code

Keywords

CMOS integrated circuits; digital signal processing chips; standards; 13.5 MIPS; 27 MHz; 40.5 MFLOPS; CPU data; DMA; DRAM; DSP56000/1 source code; IEEE 754-1985 standard; IEEE floating point DSP; VRAM; binary floating-point arithmetic; dynamic memories; fast access modes; interrupts; software-compatible; symmetric multiprocessing; CMOS process; CMOS technology; Clocks; Digital signal processing; Digital signal processing chips; Digital signal processors; Hardware; Random access memory; Read-write memory; USA Councils;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 1989. ICASSP-89., 1989 International Conference on

Conference_Location

Glasgow

ISSN

1520-6149

Type

conf

DOI

10.1109/ICASSP.1989.266970

Filename

266970