DocumentCode :
1565249
Title :
Property Specification and Static Verification of UML Models
Author :
Siveroni, Igor ; Zisman, Andrea ; Spanoudakis, George
Author_Institution :
Dept. of Comput., City Univ., London
fYear :
2008
Firstpage :
96
Lastpage :
103
Abstract :
We present a static verification tool (SVT), a system that performs static verification on UML models composed of UML class and state machine diagrams. Additionally, the SVT allows the user to add extra behavior specification in the form of guards and effects by defining a small action language. UML models are checked against properties written in a special-purpose property language that allows the user to specify linear temporal logic formulas that explicitly reason about UML components. Thus, the SVT provides a strong foundation for the design of reliable systems and a step towards model-driven security.
Keywords :
formal specification; program verification; UML models; linear temporal logic formulas; model-driven security; static verification tool; Application software; Formal verification; Logic; Object oriented modeling; Programming; Reliability; Security; Software engineering; Software systems; Unified modeling language; Model Checking; Spin; Static Verification; UML;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Availability, Reliability and Security, 2008. ARES 08. Third International Conference on
Conference_Location :
Barcelona
Print_ISBN :
978-0-7695-3102-1
Type :
conf
DOI :
10.1109/ARES.2008.194
Filename :
4529326
Link To Document :
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