Digital VLSI using parallel architecture for co-occurrence matrix determination

The co-occurrence matrices method, a statistical approach in texture analysis, has been shown to be useful in discriminating between textures. However, one limitation to this method is the computation throughput, since the matrix size is the square of the total number of grey levels. This affects the processing speed, but it can be significantly improved by parallel processing and pipelining, using specialized VLSI chips. A device using semisystolic architecture for fast co-occurrence matrix computation is presented. This device will allow the operational exploitation of statistical methods for discrimination between different textures in image processing