On efficient error-tolerability evaluation and maximization for image processing applications

With the advance of semiconductor manufacturing technology, low yield issue of a circuit/system has received much attention. Error-tolerance is an innovative concept that can significantly improve yield of integrated circuits (IC´s) by identifying defective yet acceptable chips. In this paper we first employ an Inverse Discrete Wavelet Transform (IDWT) circuit to illustrate the potential of yield improvement in a JPEG2000 decoder via error-tolerance. We then carefully analyze error distribution induced by faults in the IDWT design. The analysis results reveal that the identification of acceptable chips will be challenging and needs to be carefully addressed. We also conduct an architectural error-tolerability analysis on the target design and show that one can easily identify the internal locations where errors are unacceptable, and can therefore re-design only the circuitry associated with these locations so as to reduce the significance of errors as well as design costs. In addition we also discuss possible image post-processing methods to further increase the acceptability of the designs.