A 3X-oversampling hybrid clock and data recovery circuit with programmable bandwidth

Author

Jia-An Jheng ; Wei-Sung Chang ; Tai-Cheng Lee

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ. Taipei, Taipei, Taiwan

fYear

2014

fDate

28-30 April 2014

Firstpage

1

Lastpage

4

Abstract

A 3X-oversampling hybrid clock and data recovery (CDR) circuit with programmable bandwidth has been fabricated in a 55-nm CMOS technology. The jitter tolerance analysis and the design of the proposed architecture are presented. The proposed hybrid CDR consists of a conventional phase-tracking CDR and a oversampling CDR for jitter tolerance improvement. Based on the input jitter magnitude and jitter tolerance specification requirements, different bandwidths will be selected. The measured results of jitter tolerance are 1.2 UI @ 10 MHz, 5.5 UI @ 1 MHz, and 35 UI @ 100 kHz, respectively. The total area of this design is 0.98 mm², and the power consumption is 46.2 mW at 5-Gb/s input data rate from a 1.1V supply voltage.

Keywords

CMOS digital integrated circuits; CMOS integrated circuits; clock and data recovery circuits; jitter; power consumption; programmable circuits; tolerance analysis; CMOS technology; bit rate 5 Gbit/s; data recovery circuit; frequency 1 MHz; frequency 10 MHz; frequency 100 kHz; hybrid CDR; input jitter magnitude; jitter tolerance analysis; jitter tolerance specification requirements; oversampling hybrid clock circuit; phase-tracking CDR; power 46.2 mW; power consumption; programmable bandwidth; size 0.98 mm; size 55 nm; voltage 1.1 V; Bandwidth; Clocks; Computer architecture; Detectors; Frequency modulation; Jitter; Phase modulation;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, Automation and Test (VLSI-DAT), 2014 International Symposium on

Conference_Location

Hsinchu

Type

conf

DOI

10.1109/VLSI-DAT.2014.6834881

Filename

6834881