• DocumentCode
    1565791
  • Title

    Improving dynamic cluster assignment for clustered trace cache processors

  • Author

    Bhargava, Ravi ; John, Lizy K.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
  • fYear
    2003
  • Firstpage
    264
  • Lastpage
    274
  • Abstract
    We examine dynamic cluster assignment for a clustered trace cache processor (CTCP). Previously proposed cluster assignment techniques run into unique problems as issue width and cluster count increase. Realistic design conditions, such as variable data forwarding latencies between clusters and a heavily partitioned instruction window, increase the degree of difficulty for effective cluster assignment. The trace cache and fill unit are used to perform dynamic cluster assignment. The retire-time fill unit analysis is aided by a dynamic profiling mechanism embedded within the trace cache. This mechanism provides information about inter-trace data dependencies, an element absent in previous retire-time CTCP cluster assignment work. The strategy proposed leads to more intra-cluster data forwarding and shorter data forwarding distances. In addition, performing cluster assignment at retire time reduces issue-time complexity and eliminates early pipeline stages. This increases overall performance for integer programs by 11.5% over our base CTCP architecture. This speedup is significantly higher than a previously proposed retire-time CTCP assignment strategy. Dynamic cluster assignment is also evaluated for several alternate cluster designs as well as for media benchmarks.
  • Keywords
    cache storage; computational complexity; multiprocessing systems; pipeline processing; CTCP architecture; clustered trace cache processor; dynamic cluster assignment; dynamic profiling mechanism; instruction window; inter-trace data dependency; intra-cluster data forwarding latency; pipeline processing; retire-time fill unit analysis; time complexity; Assembly; Clustering algorithms; Data communication; Decoding; Delay; Microarchitecture; Performance analysis; Pipelines; Program processors; Programming profession;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Architecture, 2003. Proceedings. 30th Annual International Symposium on
  • ISSN
    1063-6897
  • Print_ISBN
    0-7695-1945-8
  • Type

    conf

  • DOI
    10.1109/ISCA.2003.1207006
  • Filename
    1207006