Title :
A passive supply-resonance suppression filter utilizing inductance-enhanced coupled bonding-wire coils
Author :
Hayashi, Teruaki ; Miura, Naruhisa ; Yoshikawa, Kenichi ; Nagata, M.
Author_Institution :
Kobe Univ., Kobe, Japan
Abstract :
This paper presents a low-power and compact passive supply-resonance (SR) suppression filter. By using an on-chip waveform monitor, a power-delivery network (PDN) impedance including package, and board PDNs is in-situ analyzed to identify the SR frequency fSR. A notch filter which consists of coupled bonding-wire coils and an on-chip MOS capacitor bank is auto-tuned for the SR suppression. This passive filtering approach reduces the power loss to 1/5~1/10 and the static power to effectively zero as compared to an active SR suppression circuit [1]. The coupled bonding-wire coil enhances its self-inductance and hence shrinks the on-chip capacitor size for the layout-area saving. A 0.18μm CMOS test chip demonstrates SR suppression by >43% with only <;7% of power loss and <;0.034mm layout area penalty.
Keywords :
CMOS integrated circuits; MOS capacitors; coils; low-power electronics; notch filters; passive filters; CMOS test chip; PDN impedance; SR frequency; SR suppression filter; active SR suppression circuit; inductance-enhanced coupled bonding-wire coils; layout-area saving; low-power filter; notch filter; on-chip MOS capacitor bank; on-chip waveform monitor; passive supply-resonance suppression filter; power loss reduction; power-delivery network; self-inductance; size 0.18 mum; Coils; Inductance; Noise; Passive filters; Power harmonic filters; System-on-chip; Wires;
Conference_Titel :
VLSI Design, Automation and Test (VLSI-DAT), 2014 International Symposium on
Conference_Location :
Hsinchu
DOI :
10.1109/VLSI-DAT.2014.6834894