A Voltage Balancing Method and its Stability Boundary for Five-Level Diode-Clamped Multilevel Converters

This paper presents a simple and novel current flow model for five level diode-clamped multilevel converters (DCMC). The modeling approach is independent of the modulation strategy and predicts all states of the converter based on the instantaneous values of the output current, dc-link voltages and switching states, and provides a new understanding of voltage sharing accessibility among the dc link capacitors in general. An immediate conclusion is that the ordinary sinusoidal pulse width modulation (SPWM) fails to provide a voltage balancing solution. A further important contribution of this paper is the development of an optimized space vector modulation (SVM) switching strategy to balance the capacitors´ voltages for 5-level DCMCs, a goal that was not reached for converters of 5 levels and more due to the complexity of the DCMC topology. To validate the feasibility of the proposed voltage balancing scheme, the paper presents analytical and simulation results obtained from a 5-level DCMC . In particular, the paper presents a stability region within which the voltage balancing strategy converges.