Fast Boolean matching for field-programmable gate arrays

A key step in technology mapping for non-lookup-table (such as multiplexer) based FPGAs (field programmable gate arrays) is to determine whether a given function can be implemented by the logic module. A new algorithm is presented for solving this problem. The algorithm is based on a character string representation of binary decision diagrams. Such representation leads to a matching algorithm which requires only a few string comparisons for each matching operation. When compared to the matching algorithm by searching for isomorphism on all different BDDs (binary decision diagrams), the new algorithm is much faster with a modest increase of memory requirement. For example, the experimental results showed that in matching all three-input Boolean function against Actel´s ACT1 logic module, the new algorithm is 634 times faster by using 19.9% more memory