Design and prototyping a Fast Hadamard Transformer for WCDMA

Author

Bahl, Sanat Kamal

Author_Institution

Dept. of Comput. Sci. & Electr. Eng., Univ. of Maryland Baltimore County, MD, USA

fYear

2003

Firstpage

134

Lastpage

140

Abstract

In this paper, the design and implementation of a Fast Hadamard Transformer (FHT) on a field programmable gate array (FPGA) is described. Two possible schemes which use 256 and 16 chip input sequences are compared on a Xilinx Virtex-E XCV1000E FPGA. The results indicate that the 16 chip sequence achieves 90% reduction in hardware resources and more than double the maximum frequency of operation as compared to 256 chip sequences. An application of the proposed FHT design used to perform cell search for Wideband Code Division Multiple Access (WCDMA) system is also presented.

Keywords

Hadamard transforms; code division multiple access; discrete Fourier transforms; field programmable gate arrays; logic CAD; 16 chip input sequence; 256 chip input sequence; DFT; FHT design; FHT prototyping; Fast Hadamard Transformer; WCDMA system; Wideband Code Division Multiple Access; Xilinx Virtex-E XCV1000E FPGA; cell search processor; discrete Fourier transform; field programmable gate array; hardware resource minimization; hardware resource reduction; Clocks; Computer science; Counting circuits; Discrete Fourier transforms; Error correction; Error correction codes; Multiaccess communication; Prototypes; Shift registers; Signal processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Rapid Systems Prototyping, 2003. Proceedings. 14th IEEE International Workshop on

ISSN

1074-6005

Print_ISBN

0-7695-1943-1

Type

conf

DOI

10.1109/IWRSP.2003.1207040

Filename

1207040