Hardware evaluation of low power communication mechanisms for transport-triggered architectures

The requirement for flexibility in IP-based designs increases the attractiveness of transport-triggered architectures as a suitable alternative to classic operation-triggered processors. Since the performance of these architectures strongly depends on the communication mechanism, the optimization of the bus structure represents a major design concern. In this work, a rapid prototyping methodology is employed in order to compare the power consumption and hardware requirements of several competing communication alternatives. Therefore, a generic test processor has been prototyped onto an FPGA. By monitoring the switching activity and bus statistics under realistic operation conditions, a fast and accurate evaluation of different bus coding schemes has been achieved.