Title :
Projective Geometry and precedence constraint based application mapping on multicore network-on-chip systems
Author :
Porwal, Janak ; Diwale, Sanket ; Kumar, Vinay B. Y. ; Patkar, Sachin B.
Author_Institution :
Dept. of Electr. Eng., Indian Inst. of Technol. Bombay, Mumbai, India
Abstract :
In this paper we address the problems of mapping (spatial distribution) and scheduling (temporal distribution) of tasks of an application over multiple computational units or cores. Algorithms for these are chiefly of two kinds - one, mapping followed by scheduling and two - unified mapping and scheduling. In this paper, we explore a new network topology based on Projective Geometry (PG). We develop a precedence constrained scheduling based greedy algorithm to solve the combined mapping and scheduling problem. The algorithm is shown to perform better than other state of the art approches on large problem sizes. We also compare the efficiency of the algorithm on Mesh and PG networks and show that the PG network results in much better solutions (in terms of schedule makespan and link utilization). We propose the use of PG network topology combined with a simple greedy algorithm for designing highly efficient manycore network-on-chip (NoC) system.
Keywords :
greedy algorithms; network topology; network-on-chip; scheduling; greedy algorithm; mesh networks; multicore network-on-chip systems; multiple computational units; network topology; precedence constrained scheduling; projective geometry; spatial distribution; temporal distribution; unified mapping; unified scheduling; Job shop scheduling; Network topology; Processor scheduling; Program processors; Schedules; Topology; Mesh; Network-on-chip; Perfect Difference Set; Precedence Constrained Scheduling; Projective Geometry; Unified Mapping and Scheduling;
Conference_Titel :
VLSI Design, Automation and Test (VLSI-DAT), 2014 International Symposium on
Conference_Location :
Hsinchu
DOI :
10.1109/VLSI-DAT.2014.6834911