Mixed Signal Synchronous Rectification Scheme for Current-type Resonant Converters

Timing of synchronous rectifier (SR) gating signals for resonant converters in low voltage applications is of paramount importance if high efficiency is to be maintained. Further, to operate at frequencies in the megahertz range, the problems associated with layout parasitics, and individual integrated circuit (IC) delays must be mitigated. Power application specific integrated circuits (PASICs) overcome the aforementioned problems leading to improved performance, minimized component count, and a physically smaller converter. In this paper, a synchronous rectifier logic scheme for current- type resonant converters suitable for PASIC implementation is presented. Through simulation results, it will be shown that the proposed circuit minimizes diode conduction, and provides shoot-through protection to offer an efficient, reliable solution.