Title :
Practical electrical parameter aware methodology for analog designers with emphasis on LDE aware for devices
Author :
Hau-Yung Chen ; Ming Juan ; Hsin-Hao Chen ; Guan, Arvin
Author_Institution :
Synopsys, Mountain View, CA, USA
Abstract :
The device layout structure has proven to have profound effects to its electrical characteristics for advanced technology nodes, which, if not taken into account during the design cycle, will have devastating impact to the circuit functionality. A new design methodology is presented in this paper, which can help circuit designers identify early in the design stage the performance implication due to shift of critical device instance parameters from its layout.
Keywords :
analogue integrated circuits; integrated circuit layout; LDE aware; analog designers; circuit functionality; device layout structure; electrical characteristics; electrical parameter aware methodology; layout dependent effect; Foundries; Layout; Noise; Performance evaluation; Routing; Wiring; Analog Desig; Design Methodology; Device Characteristics; Electrical Parameters; LDE; Layout Effect;
Conference_Titel :
VLSI Design, Automation and Test (VLSI-DAT), 2014 International Symposium on
Conference_Location :
Hsinchu
DOI :
10.1109/VLSI-DAT.2014.6834922
