Title :
State assignment for finite state machines using T flip-flops
Author_Institution :
Forschungszentrum Inf., Karlsruhe, Germany
Abstract :
Considerable progress in the area of state assignment for PLA and multi-level finite state machine realizations was made in the last ten years. Although many finite state machines can be more efficiently implemented if T flip-flops are used as memory elements, research has concentrated on finite state machines using D flip-flop memory. A state assignment algorithm for finite state machines using T flip-flops is presented. For realistic benchmarks, the area requirements of the finite state machine realization are up to 50% smaller if T flip-flops are used as memory elements
Keywords :
finite state machines; flip-flops; integrated memory circuits; logic CAD; logic design; optimisation; programmable logic arrays; state assignment; PLA; T flip-flops; benchmarks; coding constraints; embedding algorithm; multi-level finite state machine; optimisation; state assignment; Algorithm design and analysis; Automata; Circuit synthesis; Design automation; Flip-flops; Input variables; Programmable logic arrays; Switching circuits;
Conference_Titel :
Design Automation Conference, 1993, with EURO-VHDL '93. Proceedings EURO-DAC '93., European
Conference_Location :
Hamburg
Print_ISBN :
0-8186-4350-1
DOI :
10.1109/EURDAC.1993.410667
