Title :
Technology independent boundary scan synthesis (design flow issues)
Author :
Robinson, Markus F.
Author_Institution :
Synopsys Inc., Mountain View, CA, USA
Abstract :
A design flow paradigm that integrates technology independent boundary scan synthesis into a chip design methodology is presented. The approach accommodates multiple vendor boundary scan technologies and the requirements of (sometimes non-1149.1-compliant) user specified boundary scan architectures. Boundary scan synthesis is described and design-specific requirements, 1149.1 compliance verification, boundary scan manufacturing test, and interfacing with the board and system test environments are discussed
Keywords :
boundary scan testing; design for testability; integrated circuit testing; printed circuit testing; production testing; 1149.1 compliance verification; boundary scan manufacturing test; boundary scan synthesis; design flow; interfacing; user specified boundary scan architectures; Chip scale packaging; Circuit testing; Decoding; Logic testing; Manufacturing industries; Process design; Protocols; Registers; Standards development; System testing;
Conference_Titel :
Design Automation Conference, 1993, with EURO-VHDL '93. Proceedings EURO-DAC '93., European
Conference_Location :
Hamburg
Print_ISBN :
0-8186-4350-1
DOI :
10.1109/EURDAC.1993.410670
