Title :
A low-power CMOS analog voltage buffer using compact adaptive biasing
Author :
Sawigun, Chutham ; Mahattanakul, Jirayuth ; Demosthenous, Andreas ; Pal, Dipankar
Author_Institution :
Dept. of Electron. Eng., Mahanakorn Univ. of Technol., Bangkok
Abstract :
A CMOS analog buffer with high output drivability is presented. The buffer combines class-AB operation with rail-to-rail signal swing. A new adaptive biasing scheme is proposed with low complexity, thereby allowing the construction of a very compact, low-power analog voltage buffer with wide bandwidth and high slew rate. Simulated results using a 0.35-mum CMOS process are provided. The circuit operates from a single 1.5-V power supply and has a quiescent power consumption of only 282 muW.
Keywords :
CMOS analogue integrated circuits; buffer circuits; low-power electronics; CMOS; adaptive biasing scheme; low-power analog voltage buffer; power 282 muW; size 0.35 micron; voltage 1.5 V; Bandwidth; CMOS process; CMOS technology; Circuit simulation; Educational institutions; Energy consumption; Power supplies; Rail to rail operation; Variable structure systems; Voltage;
Conference_Titel :
Circuit Theory and Design, 2007. ECCTD 2007. 18th European Conference on
Conference_Location :
Seville
Print_ISBN :
978-1-4244-1341-6
Electronic_ISBN :
978-1-4244-1342-3
DOI :
10.1109/ECCTD.2007.4529521
