TONIC: A timing database for VLSI design

Author

Schulte, Gregory ; Tong, Peter ; Rusu, Stefan ; Taylor, Stuart

Author_Institution

Sun Microsystems, Inc., Mountain View, CA, USA

fYear

1993

Firstpage

426

Lastpage

431

Abstract

A unified timing database for VLSI (very large scale integration) design is presented. The approach has been successfully used for the design of a three million transistor microprocessor. The database and timing methodology are oriented towards, but not restricted to, the top-down design style. Emphasis is placed upon integration with other timing tools such as circuit simulators, logic synthesis tools, and static timing analyzers

Keywords

VLSI; circuit CAD; integrated circuit design; logic CAD; logic design; microprocessor chips; timing; TONIC; VLSI design; circuit simulators; logic synthesis; microprocessor; net timing; pin timing; static timing analyzers; timing database; timing methodology; timing tools; top-down design style; Distributed databases; Financial management; Integrated circuit modeling; SPICE; Spatial databases; Sun; Timing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1993, with EURO-VHDL '93. Proceedings EURO-DAC '93., European

Conference_Location

Hamburg

Print_ISBN

0-8186-4350-1

Type

conf

DOI

10.1109/EURDAC.1993.410672

Filename

410672

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1567326