A RISC CPU IP core

This article describes the hardware design of a RISC CPU IP core whose instructions are compatible with the Microchip PIC16C6X-series of microcontrollers. In this paper, an 8-bit CPU based on RISC architecture is designed by Top-Down IC design method. The RISC CPU core is based on Harvard architecture with 14-bit instruction length and 8-bit data length and two-stage instruction pipeline. The performance of the RISC MCU has been improved by replacing micro-program with direct logic block. As a result, most of the instructions only need one machine cycle to be executed except those related to program branches, and the speed is increased. Since this type of CPU based on RISC architecture, there are only 35 reduced instructions in its instruction set, which are easy to be learned and used. The performance of the 8-bit RISC CPU is better than those of CPUs which are based on CISC architecture. It can be widely used in those controlling fields demanding low power consumption and high ratio of performance to price.