Hierarchical test generation: Where we are, and where we should be going

Complex VLSI (very large scale integration) system design with VHDL requires test generation techniques that work at different levels in the abstraction hierarchy. The author discusses approaches to test generation which attempt to address this issue. Areas of test generation considered are behavior-assisted gate-level and switch-level test generation, test construction from sub-component tests, and test generation from behavioral models. The status of these methods and recommendations for future research and development are given, so that effective hierarchical test generation can become a reality