The design of clock distribution in the parallel/interleaved sampling system

Author

Peng, Cao ; Mingfei, Wang ; Wei, Qi ; Yuanchun, Fei ; Haiyan, Tian ; Fanjun, Meng

Author_Institution

Sch. of Inf. & Mech. Eng., Beijing Inst. of Graphic Commun., Beijing, China

fYear

2009

Abstract

The paper introduced the mathematical model in both time and frequency domain of parallel/interleaved sampling system, the total gain error, phase shift error, aperture jitter error of multi-channel sampling scheme are all involved. The critical layout techniques of a hi-speed and hi-resolution analog-to-digital conversion circuit are also provided. At last, a 4-channel interleaved sampling clock circuit with the jitter level of sub-picosecond is given, whose phase noise and jitter test results are also shown.

Keywords

analogue-digital conversion; phase noise; signal sampling; timing jitter; analog-to-digital conversion circuit; aperture jitter error; clock distribution; gain error; multichannel sampling; parallel/interleaved sampling; phase noise; phase shift error; Circuits; Clocks; Computer errors; Instruments; Jitter; Phase measurement; Phase noise; Sampling methods; Signal processing; Signal sampling; clock distribution; jitter; parallel/interleaved A/D converter; phase noise;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Measurement & Instruments, 2009. ICEMI '09. 9th International Conference on

Conference_Location

Beijing

Print_ISBN

978-1-4244-3863-1

Electronic_ISBN

978-1-4244-3864-8

Type

conf

DOI

10.1109/ICEMI.2009.5274809

Filename

5274809