Module generation based VLSI implementation of a demultiplexer for satellite communications

The VLSI implementation of a digital demultiplexer for on-board satellite communication is presented. The demultiplexer is used to separate the frequency division multiple access signals into individual channels. The architecture has two modules namely polyphase filter module and a FFT module operating in pipeline fashion. Architecture and the VLSI implementation for demultiplexing 800 channels have been developed and simulated. A module generation scheme is used that has advantages over the full custom approach with automated generation techniques. The module generation scheme uses a flexible cell based design. It has an advantage of being flexible, efficient and reliable. Various CAD tools from Mentor Graphics and 0.8 micron CMOS process from Hewlett Packard have been used for the layout