Title :
Applying a seamless design flow to fast development of a carrier synchronizer for MPSK
Author :
Vaupel, M. ; Meyr, H.
Author_Institution :
Aachen Univ. of Technol., Germany
Abstract :
Short product cycles and the necessity to achieve a short time to market call for sophisticated design methodologies. In this paper a seamless design flow is described enabling the design of engineering a chip for carrier synchronization of 8PSK, QPSK and BPSK modulated signals in three months. The circuit was fabricated in a 1 μm CMOS process using standard cells and is currently in commercial use in a modem for digital TV transmission
Keywords :
CMOS digital integrated circuits; application specific integrated circuits; cellular arrays; digital phase locked loops; digital television; modems; phase shift keying; quadrature phase shift keying; synchronisation; television transmitters; 1 micron; 8PSK; BPSK; CMOS process; MPSK; QPSK; carrier synchronizer; digital PLL; digital TV transmission; modem; product cycles; seamless design flow; standard cells; time to market; Binary phase shift keying; CMOS process; Circuits; Design engineering; Design methodology; Digital TV; Modems; Quadrature phase shift keying; Signal design; Time to market;
Conference_Titel :
VLSI Signal Processing, VIII, 1995. IEEE Signal Processing Society [Workshop on]
Conference_Location :
Sakai
Print_ISBN :
0-7803-2612-1
DOI :
10.1109/VLSISP.1995.527484
