• DocumentCode
    1568434
  • Title

    The concept of superprocesses for high-level synthesis and their VHDL modelling

  • Author

    Keresztes, P. ; Agotai, Istvá N.

  • Author_Institution
    Kando Kalman Polytech., Budapest, Hungary
  • fYear
    1993
  • Firstpage
    480
  • Lastpage
    485
  • Abstract
    The authors describe a process with a concurrent control flow as a superprocess. A combined VHDL and data/control flow graph description is proposed so as to create abstract level behavioral specifications containing a concurrent control flow. The functions of the simulation compiler are exposed
  • Keywords
    concurrency control; data flow computing; data flow graphs; hardware description languages; high level synthesis; logic design; multiprocessing systems; program compilers; VHDL modelling; abstract level behavioral specifications; concurrent control flow; data/control flow graph; high-level synthesis; simulation compiler; superprocesses; Books; Computer languages; Concurrent computing; Control system synthesis; Flow graphs; Hardware design languages; High level synthesis; Natural languages; Parallel algorithms;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 1993, with EURO-VHDL '93. Proceedings EURO-DAC '93., European
  • Conference_Location
    Hamburg
  • Print_ISBN
    0-8186-4350-1
  • Type

    conf

  • DOI
    10.1109/EURDAC.1993.410680
  • Filename
    410680
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1568434