Title :
Synchronous designs in VHDL
Author :
Debreil, Alain ; Oddo, Philippe
Author_Institution :
BULL SA, Les Clayes-sous-Bois, France
Abstract :
Previously, the authors (Proc. Euro. Design Automat. Conf., pp. 680-681, 1992) defined how the concept of synchronous design can be mapped to VHDL descriptions. Now, they present a set of rules, such that, if respected, the VHDL description is synchronous. They then extend the strict notion of synchronism to circuits that can be resynchronized assuming some good timing property and introduce the concept of cleanliness for this purpose
Keywords :
combinational circuits; hardware description languages; logic CAD; logic design; synchronisation; timing; VHDL; cleanliness; combinational logic; synchronous design; timing property; Automata; Circuit stability; Circuit synthesis; Clocks; Design automation; Flip-flops; Hardware design languages; Signal design; Synchronization; Timing;
Conference_Titel :
Design Automation Conference, 1993, with EURO-VHDL '93. Proceedings EURO-DAC '93., European
Conference_Location :
Hamburg
Print_ISBN :
0-8186-4350-1
DOI :
10.1109/EURDAC.1993.410681
