Resilient design in scaled CMOS for energy efficiency

Traditional processors are designed to guarantee error-free operation under worst-case device & interconnect parameter variations resulting from less than ideal manufacturing process control; static & erratic defects; operating environments such as temperature excursions and voltage droops; critical path activation and path delay degradations due to multiple inputs switching simultaneously in gates containing transistor stacks, or signal coupling from neighboring lines in interconnect paths; speed degradation over the operating lifetime due to transistor aging under voltage, temperature & current stress; early-life failures due to latent defect accelerations; and soft error due to cosmic rays and alpha particle impacts. The voltage-frequency settings for all processors are set based on these infrequently encountered worst-case considerations, even though under typical conditions voltage can be pushed down further or frequency increased without causing errors for most of the processors, thus limiting both energy efficiency and performance in scaled CMOS technologies.