Title :
Bounded potential slack: Enabling time budgeting for dual-Vt allocation of hierarchical design
Author :
Seomun, Jun ; Paik, Seungwhun ; Shin, Youngsoo
Author_Institution :
Dept. of Electr. Eng., KAIST, Daejeon, South Korea
Abstract :
Time budgeting, which assigns timing assertion at block boundary, is a crucial step in hierarchical design. The proportion of high- and low-Vt gates of each block, which determines overall leakage power consumption, is dictated by timing assertion, yet dual-Vt allocation is not taken into account during conventional time budgeting. Bounded potential slack is introduced as a measure of dual-Vt allocation, and is experimentally shown to be strongly correlated with the percentage of high-Vt gates. A new time budgeting is proposed with objective of achieving bounded potential slack, which is formulated as a linear programming problem. In experiments with example hierarchical designs implemented in 45-nm commercial technology, the proposed time budgeting reduced leakage power by 32% on average compared to conventional time budgeting, when both are followed by the same dual-Vt allocation. The time budgeting is also applied to voltage island design, where each block can have its own Vdd with mix of high- and low-Vt gates.
Keywords :
VLSI; linear programming; logic arrays; logic design; power consumption; system-on-chip; bounded potential slack; dual-Vt allocation; hierarchical design; high-Vt gates; linear programming problem; low-Vt gates; overall leakage power consumption; size 45 nm; time budgeting; timing assertion; Delay effects; Delay estimation; Energy consumption; Linear programming; Microprocessors; System-on-a-chip; Timing; Very large scale integration; Voltage; Wiring;
Conference_Titel :
Design Automation Conference (ASP-DAC), 2010 15th Asia and South Pacific
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-5765-6
Electronic_ISBN :
978-1-4244-5767-0
DOI :
10.1109/ASPDAC.2010.5419817