Title :
Architectural synthesis of an image processing algorithm using IRIS
Author :
Trainor, D.W. ; Woods, R.F. ; McCanny, J.V.
Author_Institution :
Inst. of Adv. Microelectron., Queen´´s Univ., Belfast, UK
Abstract :
Details are presented of the IRIS synthesis system for high-performance digital signal processing. This tool allows non-specialists to automatically derive VLSI circuit architectures from high-level, algorithmic representations, and provides a quick route to silicon implementation. The applicability of the system is demonstrated using the design example of a one-dimensional Discrete Cosine Transform circuit
Keywords :
VLSI; circuit CAD; digital signal processing chips; discrete cosine transforms; high level synthesis; image processing; integrated circuit design; IRIS synthesis; VLSI circuit architecture; digital signal processing; image processing algorithm; one-dimensional discrete cosine transform; Circuit synthesis; Digital signal processing; Discrete cosine transforms; Hardware; Image processing; Iris; Signal processing algorithms; Signal synthesis; Silicon; Very large scale integration;
Conference_Titel :
VLSI Signal Processing, VIII, 1995. IEEE Signal Processing Society [Workshop on]
Conference_Location :
Sakai
Print_ISBN :
0-7803-2612-1
DOI :
10.1109/VLSISP.1995.527488
