Title :
Application-specific 3D Network-on-Chip design using simulated allocation
Author :
Zhou, Pingqiang ; Yuh, Ping-Hung ; Sapatnekar, Sachin S.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Minnesota, Minneapolis, MN, USA
Abstract :
Three-dimensional (3D) silicon integration technologies have provided new opportunities for Network-on-Chip (NoC) architecture design in Systems-on-Chip (SoCs). In this paper, we consider the application-specific NoC architecture design problem in a 3D environment. We present an efficient floorplan-aware 3D NoC synthesis algorithm, based on simulated allocation, a stochastic method for traffic flow routing, and accurate power and delay models for NoC components. We demonstrate that this method finds greatly improved topologies for various design objectives such as NoC power (average savings of 34%), network latency (average reduction of 35%) and chip temperature (average reduction of 20%).
Keywords :
application specific integrated circuits; integrated circuit design; network topology; network-on-chip; three-dimensional integrated circuits; NoC; application-specific 3D network-on-chip design; stochastic method; three-dimensional silicon integration technologies; topologies; traffic flow routing; Delay; Network synthesis; Network topology; Network-on-a-chip; Power system modeling; Routing; Silicon; Stochastic processes; Telecommunication traffic; Traffic control;
Conference_Titel :
Design Automation Conference (ASP-DAC), 2010 15th Asia and South Pacific
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-5765-6
Electronic_ISBN :
978-1-4244-5767-0
DOI :
10.1109/ASPDAC.2010.5419830
