Buffered clock tree sizing for skew minimization under power and thermal budgets

In this paper, we study the clock tree sizing problem for thermal-aware skew minimization under power and thermal budgets. Clock wire/buffer sizing affects not only the delay/skew, but also the power dissipation of the clock tree. This effect in turn triggers changes in thermal distribution, making re-computation of the delay/skew necessary. Thus, the interaction among skew, power, and temperature is highly complicated if tied with clock wire/buffer sizing. In order to efficiently combat the time-varying nature of underlying thermal profile, we focus on two kinds of skew, depending on the number of thermal profiles given: skew value and skew range. The former refers to the skew value computed under a single steady-state thermal profile, whereas the latter refers to the skew range computed based on multiple thermal profiles. Our thermal-aware sequential-linear-programming approach maintains near-zero skew value and narrow skew range while keeping the power dissipation and temperature under the given budgets.