Yield modeling and assessment for nanocrossbar systems

Crossbar architectures are promising in the emerging nanoelectronic environment, yet suffer from massive defects. Defect-tolerant logic mapping emerges as a new challenging process in constructing nanocrossbar-based architectures. New yield models and metrics need to be developed to evaluate the logic mapping process, due to the complexity involved in searching for a valid mapping. We show the traditional concept of yield becomes unrealistic due to the lack of consideration for runtime cost, and present a new mapping-aware yield model. Furthermore, we provide assessment of defect-tolerant logic mapping from the perspective of mismatch number distribution. It turns out that such mismatch number distribution serves as a solid basis on understanding the various new factors involved in the logic mapping process.