DocumentCode
1569070
Title
Design and verification methods of toshiba´s wireless LAN baseband SoC
Author
Kuwahara, Masanori
Author_Institution
Wireless Network SoC Dept., Toshiba Corp. Semicond. Co., Kawasaki, Japan
fYear
2010
Firstpage
457
Lastpage
463
Abstract
This paper presents design and verification methods of Toshiba´s wireless LAN (WLAN) baseband SoCs. An FPGA-based high-speed and reliable verification environment for physical layer (PHY), a new SDL-based hardware design method for media access control layer (MAC), and an ultra low power design resulting in power consumption of 22 uW in the deep-sleep mode are described.
Keywords
access protocols; field programmable gate arrays; logic design; system-on-chip; wireless LAN; SDL based hardware design method; Toshiba wireless LAN baseband SoC; deep-sleep mode; field programmable gate array; media access control layer; physical layer; power 22 muW; power consumption; system-on-chip; wireless local area nework; AWGN; Baseband; Circuit testing; Design methodology; Field programmable gate arrays; Media Access Protocol; Modems; Physical layer; Signal processing algorithms; Wireless LAN;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference (ASP-DAC), 2010 15th Asia and South Pacific
Conference_Location
Taipei
Print_ISBN
978-1-4244-5765-6
Electronic_ISBN
978-1-4244-5767-0
Type
conf
DOI
10.1109/ASPDAC.2010.5419840
Filename
5419840
Link To Document