Title :
A net-based semantics for VHDL
Author :
Damm, W. ; Josko, B. ; Schlör, R.
Author_Institution :
Dept. of Comput. Sci., Oldenburg Univ., Germany
Abstract :
The VHDL standard gives only an informal description of the semantics of VHDL. To apply formal verification techniques, a precise semantics definition is necessary. A formal semantics for VHDL based on interpreted Petri nets is defined. The presented semantics is compositional and provides a link to automatic verification methods for VHDL based designs
Keywords :
Petri nets; formal specification; formal verification; hardware description languages; logic CAD; logic design; VHDL; automatic verification; formal semantics; formal verification; informal description; interpreted Petri nets; net-based semantics; semantics; standard; Automatic logic units; Computer science; Delay; Design methodology; Formal verification; High level synthesis; Logic design; Petri nets; Standards development; Timing;
Conference_Titel :
Design Automation Conference, 1993, with EURO-VHDL '93. Proceedings EURO-DAC '93., European
Conference_Location :
Hamburg
Print_ISBN :
0-8186-4350-1
DOI :
10.1109/EURDAC.1993.410685
