Title :
Temporal circuit partitioning for a 90nm CMOS multi-context FPGA and its delay measurement
Author :
Miyamoto, Naoto ; Ohmi, Tadahiro
Author_Institution :
New Ind. Creation Hatchery Center, Tohoku Univ., Sendai, Japan
Abstract :
In this paper, we present a dynamically reconfigurable multi-context FPGA named Flexible Processor (FP) equipped with shift-register temporal communication module (SR-TCM). Temporal partitioning algorithm has been developed, which divides a long critical path into equal-length short paths context-wise. From measurement results of a FP fabricated by using a 90 nm CMOS technology, it is found that the execution latency remains constant regardless of the number of contexts used.
Keywords :
CMOS integrated circuits; field programmable gate arrays; CMOS multicontext FPGA; delay measurement; flexible processor; reconfigurable multicontext FPGA; shift-register temporal communication module; size 90 nm; temporal circuit partitioning; temporal partitioning; Capacitance; Circuit synthesis; Clocks; Delay; Field programmable gate arrays; Minimization; Network synthesis; Robustness; Routing; Wire;
Conference_Titel :
Design Automation Conference (ASP-DAC), 2010 15th Asia and South Pacific
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-5765-6
Electronic_ISBN :
978-1-4244-5767-0
DOI :
10.1109/ASPDAC.2010.5419855
