Title :
Design and chip implementation of an instruction scheduling free ubiquitous processor
Author :
Fukase, Masa-aki ; Murakami, Ryosuke ; Sato, Tomoaki
Author_Institution :
Grad. Sch. of Sci. & Tech., Hirosaki Univ., Hirosaki, Japan
Abstract :
Instruction scheduling is a crucial issue for cutting edge VLSI processors that exploit parallelism to solve the tradeoff between clock speed and power dissipation. A double scheme for multiple pipelines merges their scalar units into a multifunctional unit (MFU) and makes the MFU wave-pipeline. Parallelizing a resultant pipeline achieves instruction scheduling free due to multifunctionality. Applied such approach to the latest design of a ubiquitous processor, HCgorilla, this is implemented by using 0.18-¿m CMOS standard cell chip.
Keywords :
VLSI; logic design; microprocessor chips; pipeline processing; processor scheduling; CMOS standard cell chip; HCgorilla ubiquitous processor; chip implementation; cutting edge VLSI processors; free ubiquitous processor; instruction scheduling; multifunctional unit; multiple pipelines; parallelism; ship design; size 0.18 mum; Arithmetic; CMOS process; Clocks; Delay; Hardware; Java; Parallel processing; Pipelines; Processor scheduling; Very large scale integration;
Conference_Titel :
Design Automation Conference (ASP-DAC), 2010 15th Asia and South Pacific
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-5765-6
Electronic_ISBN :
978-1-4244-5767-0
DOI :
10.1109/ASPDAC.2010.5419856
